1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device that includes memory cells that are memory transistors each having a charge storing layer and a control gate, and a method for manufacturing such a nonvolatile semiconductor memory device.
2. Related Art
As the memory cells for electrically rewritable nonvolatile semiconductor memory devices (EEPROM), there have been known memory cells called NAND flash memories each having a MOS transistor structure that includes a charge storing layer and a control gate in its gate unit, and injects charges into the charge storing layer and releases charges from the charge storing layer with the use of a tunnel current. In each of those memory cells, threshold voltages representing different charge storing states of the charge storing layer are stored as the data “0” and “1”. For example, to inject electrons into a floating gate that is the charge storing layer, the substrate is grounded, and a positive high voltage is applied to the control gate. Electrons are then injected into the floating gate from the substrate side, by virtue of the tunnel current. As a result of the electron injection, the threshold voltage of the memory cell shifts in the positive direction. To release electrons from the floating gate, the control gate is grounded, and a positive high voltage is applied to the source/drain diffusion layer or the substrate. Electrons are then released from the floating gate toward the substrate, by virtue of the tunnel current. As a result of the electron release, the threshold voltage of the memory cell shifts in the negative direction.
However, in today's highly sophisticated information society and in the trend of rapid digitalization, those nonvolatile semiconductor memory devices have been rapidly becoming minute and have higher capacities. As the nonvolatile semiconductor memory devices become minute, more problems arise, such as short-channel effects, intercell interference effects, and difficulties in manufacturing. As a result, the product development is becoming more and more difficult. Particularly, short-channel effects are one of the biggest problems, causing deterioration in ON/OFF ratio and degrading the performance of each memory. Therefore, memory cells that have fully-depleted (FD) channel structures resistant to short-channel effects have been suggested (see JP-A 2000-174241 (KOKAI), for example).
If a structure becomes as small as where the distance between each two cells is 32 nm or less, it is technically difficult to form a source and drain between the cells.